CS501-Advanced Computer Architecture Quiz MCQS #Objective #Questions #MidTerm
1. SPARC uses a simple set of ___ instruction formats.
- 64-bit ✔
- 12-bit
- 16-bit
- 32-bit
2. From an n bit control word we may have ___ bit signal values
- 2^n ✔
- n^2
- n x n
- 2 x n
3. While executing the RTL instruction A←R3, which of the given below control signals will be activated?
- LA, R3in ✔
- R3out
- LA, R3out
- R3in, Lout
4. The multiplexer ___ is used to decide which value is transferred to be written back to the register file
- MP2
- MP3
- MP4
- MP5 ✔
5. ___ is defined as the number of instructions processed per second
- Memory Access
- Throughput ✔
- ALU Operations
- Latency
6. The ALSU function “INC2” increments the ___ by 2 and the output is stored in the buffer register ___
- PC, A
- IR, A
- PC, C ✔
- IR, C
7. The third stage of the Pipelined version of SRC is:
- Instruction Fetch
- ALU operation ✔
- Memory access
- Register write
8. In ___ only one field is required which specifies the type of operation
- 3-Address instruction
- 2-Address instruction
- 1-Address instruction
- 0-Address instruction ✔
9. ___ usually involves calculating the target address and evaluating a condition
- Load/Store instructions
- Branch instructions ✔
- ALU instructions
- Pipelined SRC
10. In the 3-bus Implementation for the SRC, all the special purpose as well as the general purpose registers have ___ read port(s) ___ write port(s)
- one, two
- two, one ✔
- two, two
- three, one
11. Which of the given techniques is used for overlapping the multiple instructions at one time?
- Pipelining ✔
- Branch delay
- Data forwarding
- SRC
12. An “assembler” that runs one processor and translates an assembly language program written for another processor into the machine language of the other processor is called a ___
- compiler
- cross assembler ✔
- debugger
- linker
13. To implement an N-bit barrel shifter in form of a combinational circuit, we require N ___
- multiplexers ✔
- de-multiplexers
- selectors
- tri-state buffers
14. The SRC uses a hazard detection unit. The hazard can be resolved using either pipeline stalls or by ___
- Data forwarding ✔
- Data compressing
- Instruction forwarding
- Instruction handling
15. What functionality is performed by the instruction “lar R3, 36” of SRC?
- It will load the register R3 with the contents of the memory location M [PC+36]
- It will load the register R3 with the relative address itself (PC+36) ✔
- It will store the register R3 content to the memory location M [PC+36]
- It will left rotate the value of R3, 36 times and will store the result into R3
16. To connect together five (5) m-bit registers in a point-to-point scheme. ___ connection are required.
- 25
- 30
- 20 ✔
- 24
17. Which one of the following is the correct RTL description for sign extension of an 8-bit constant?
- (8⍺IR<7>©IR<7..0>) ✔
- (8⍺IR<8>©IR<8..1>)
- (8⍺IR<7>©IR<8..0>)
- (8⍺IR<8>©IR<7..0>)
18. In the case of a constant, variable, and address or (label-PC), the unconditional jump ranges ___
- from -128 to 127 ✔
- from -64 to 63
- from -256 to 255
- from -32768 to 32767
19. Which of the following branch instruction has a condition which is always executed?
- JZ
- JUMP ✔
- JPL
- JMI
20. The instruction “PUSH A” is an example of ___
- 0-address instruction ✔
- 1-address instruction
- 2-address instruction
- 3-address instruction
21. ___ instruction is used to load a register with an immediate data value
- la ✔
- lar
- ld
- ldr
22. All of the below given processors enjoy Little-Endian storage format except ___
- EAGLE
- Modified Eagle
- Falcon-A ✔
- Falcon-E
23. CISC stands for?
- Computer instruction set compiler
- Complex instruction set compiler ✔
- Complex internal system computer
- Complex instruction system compiler
24. ret and jmi both belong to ___ type instructions
- Arithmetic
- Control ✔
- Data Transfer
- Logic
25. ___ control signal enables the input to the PC for receiving a value that is currently on the internal processor bus.
- LPC ✔
- INC4
- LC
- Cout
26. In case of SRC processor, bits ___ of IR (instruction register) are reserved for the op-code
- 0 to 4
- 11 to 15
- 27 to 31 ✔
- 59 to 63
27. Which one of the following registers holds the instruction that is being executed?
- Accumulator
- Address Mask
- Instruction Register ✔
- Program Counter
28. In any instruction the possible locations of the source operands can be ___
- CPU Registers
- Memory Cells
- I/O Locations
- All of the given ✔
29. Which of the following is not a part of processor state?
- IR
- PC
- Stack ✔
- Registers
30. ___ hazard occurs when attempting to access the same resource in different ways at the same time
- Branch
- Data
- Structural ✔
- Instruction
