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CS302-Digital Logic Design Quiz MCQs Lecture 23-45 Finalterm Objective Questions

CS302-DLD Quiz  MCQS #Objective #Questions #Finalterm

1. The terminal count of a modulus-13 binary counter is:

  • 0000
  • 1111
  • 1101
  • 1100

2. In Master-Slave flip-flop setup, the master flip flop operates at ___

  • Positive half cycle of pulse
  • Negative half cycle of pulse
  • Both Master-Slave operates simultaneously
  • Master-Slave flip-flop does not operate on pulses, rather it is edge triggered

3. The ___ input overrides the ___ input

  • Asynchronous, synchronous
  • Synchronous, asynchronous
  • Preset input (PRE), Clear input (CLR)
  • Clear input (CLR), Preset input (PRE)

4. A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power of dissipation of the flip -flop is:

  • 10mW
  • 25mW
  • 64mW
  • 1024mW

5. With a 100KHz clock frequency, eight bits can be serially entered into a shift register in

  • 80 micro seconds
  • 8 micro seconds
  • 80 mili seconds
  • 10 micro seconds

6. The 74HC163 is a 4-bit Synchronous Counter, it has ___ parallel data inputs pins

  • 2
  • 4
  • 6
  • 8

7. ___ Counters as the same indicates are not triggered simultaneously

  • Asynchronous
  • Synchronous
  • Positive-Edge triggered
  • Negative-Edge triggered

8. ___ is one of the examples of asynchronous inputs.

  • J-K input
  • S-R input
  • D input
  •  Clear input (CLR)

9. To write data to the memory, the write cycle is initiated by

  • applying the address signals
  • assigning the values to variables
  • reserving the space for variables
  • applying the data signals

10. ___ is one of the examples of synchronous inputs.

  • J-K input
  • EN input
  • Preset input (PRE)
  • Clear input (CLR)


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