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# CS302-Digital Logics and Design Assigment no. 3 Solution Spring 2018 Due Date: 30 July, 2018

CS302βDigital Logics and Design
Assignment no. 3
Semester: SPRING 2018
Total Marks: 20
Due Date: 30, July 2018

CS302-DLD Assignment #Rules for marking
It should be clear that your assignment would not get any credit if:
• The assignment is submitted after the due date.
• The submitted assignment does not open or file is corrupt.
• Strict action will be taken if submitted solution is copied from any other student or from the internet.
You should concern the recommended books to clarify your concepts as handouts are not sufficient.
You are supposed to submit your assignment in .doc or docx format.

Any other formats like scan images, PDF, zip, rar, ppt and bmp etc will not be accepted

π Recommended: Install Math Type Equation Editor

CS302-DLD Assignment Topics Covered

• ALU
• Multiplexor
• DE multiplexer
• GAL / PAL / PLA
• ABEL
CS302-DLD Assignment #Important Note

No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date.

If you people find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline no queries will be entertained in this regard.

For any query, feel free to email at:
cs302@vu.edu.pk

CS302-DLD Assignment # 3

You are provided with a figure that represents 3×4 PLA. You need to find out:

I. Boolean expression for P1, P2, P3, P4 & P5.
II. Boolean expression for Final Outputs O1, O2, O3 & O4.
III. Convert all Boolean expressions (P1, P2, P3, P4, P5, O1, O2, O3 & O4) into ABEL expressions/equations.

CS302-DLD Assignment #Video

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